CDMS II Trigger Logic Test Diagnostics
This important powerup information should be
read before powering up the logic board.
We have taken several pictures of the trigger logic board. Here they are:
- Here are a couple of shots of the board before it was stuffed with parts (
- Here are a couple shots of the new regulator. (
- Sam Burke considers the test setup.
pic 1: 1-29-2001,
- Sam Burke checks the oscilliscope.
pic 2: 1-29-2001,
- A closeup of the trigger logic board.
pic 3: 1-29-2001,
We have pictures of various tests and modifications made. Here they are:
- Here is the schematic of the first change needed to
fix the clock lines.
- The MAX688 regulator still has the
400ms 1V hump at startup.
- The MAX604 regulator had some trouble handling the startup current inrush. Here is a trace from the oscilliscope of a
successful startup. Note the 400ms long 1V hump of higher voltage at the beginning of the powerup for the 3.3V line. We don't believe this should occur. Also note that the calibration of the trace program was a little off. Thus, the voltages in this trace read .2V too higher than they should.
- Here is a trace of the output voltage from the regulator on a completely
- Here is a trace of the output voltage from the regulatr on a particularly
unusually failed startup.
- Here are before and after pictures of the trigger logic board layout from when the design was changed to add the -Read and -Write lines (
Below is an selective chronologic update of modifications:
- 11-6-01 Second trigger logic board ordered from fabrication house. Board should be available for testing in a couple weeks!!
- 10-30-01 The Orcad layout has been processed and is ready to be sent to the fabrication house for the creation of a second trigger logic board.
- 10-22-01 The Orcad layout has been updated for all the changes to the prototype board.
- 05-31-01 Learned that pins on the FPGA socket may become depressed and that line's connection to the FPGA may be lost. Solving simply requires bending the pin slight back out. This will only be a problem is the FPGAs are removed repeatedly.
- 05-11-01 Prescaling on prototype trigger logic board works correctly.
- 05-01-01 Test of new prototype trigger logic board made at SUF. The optional prescaling feature is shown to need further testing however the rest of the testing is successful!
- 02-15-01 New 8V-6A power source arrived. This means that we no longer need to jury rig 3 power sources together to supply enough current while still having current limiting. It also means that the 3 dc to dc converters, that power the opto isolator outputs for FPGAs C-H, can be soldered to the board.
- 02-15-01 Solved freezing problem. It seems that FPGA C hadn't made a good connection with its socket.
- 02-14-01 Isolated this freezing problem to FPGA C. The other FPGAs seem to handle triggers sent to them correctly.
- 02-13-01 Discovered that some triggers sent to different FPGAs via the trigger conditioner board seem to freeze the trigger and live LEDs off.
- 02-13-01 Verified that only a low level trigger will generate a global trigger, since the FPGAs are in the default (low) mode.
- 02-12-01 Was able to generate a global trigger from a simulated RTF input trigger sent to FPGA A via a trigger conditioner board.
- 02-08-01 Verified that the green LIVE led functions properly. The LIVE led indicated that the trigger logic board is enabled.
- 02-08-01 Determined that the design calls for the tantalum capacitor C3 to be backwards. Upon turning the capacitor around, the red trigger led began to behave as designed.
- 02-07-01 Realized that the SPARE trigger in and RANDOM trigger needed termination for the red trigger led to function properly, however the led stays lit when the board is powered.
- 02-07-01 Trying to get the red trigger led to work properly, realized that pin 9 on U13 needed to be tied to ground instead of 5V.
- 02-06-01 Fixed the clock lines. There were 2 corrections needed. First, pins 10 and 13 on U20 were tied to 5V instead of ground (See the modifications list). The second problem was corrected when I corrected a mistake I made on 1-25-01. On that date, I incorrectly wiring the -Read, -Write correction to U17 instead of U15.
- 02-05-01 Learned that the real and live clock lines don't clock.
- 02-05-01 Fixed pins 8 and 10 on the register.
- 01-31-01 Learned that the MAX688 also has a 400ms long 1V overshoot of higher voltage at the beginning of the 3.3V line powerup. The new 688 regulator also has the same problem with a residual voltage left on the board. However, the 688 regulator only needs about 5s for the residual voltage to decay sufficiently.
- 01-30-01 Noticed that pins 8 and 10 on the board switch register can't be pulled down.
- 01-30-01 Successfully able to read the board switch registers for the first time!
- 01-30-01 Replaced MAX604 regulator with a regulator (MAX688) that should be better able to handle the startup inrush of current.
- 01-29-01 Learned that the chips U3 and U26 were 74HC08 (AND) gates. They should be 74HC04 (inverting) chips. This problem made it impossible to read the registers.
- 01-25-01 Changed design so -Read and -Write and digitally ored going to U32 pin 19. Previously just -Write ran to pin 19 which kept precluded reading the trigger logic board.
- 01-??-01 Noticed that the red trigger led incorrectly stays lit while the board is powered up.
- 01-??-01 Discovered that there was a residual voltage left in the circuit (due to decoupling capacitance) after powering the board down that the regulator tried to powerup. The regulator would start up correctly if the residual voltage was given sufficent time (about 15s) to decay away or if it was removed by grounding the 3.3V high.
- 01-??-01 Learned that when our 3.3V regulator (MAX604) started up, the 3.3V line had a 1V overshoot for the first 400ms of the startup.
- 01-??-01 The diode at D3 drew far too much current. Replaced it with a diode that was better suited for the job.
Our engineer who designed the trigger logic board, Sam Burke, has a web page containing documentation on the trigger logic board such as diagrams, schematics, and board layouts.
For further information on the trigger logic board, email firstname.lastname@example.org
Last updated 10-03-02.