Neutron Trigger Changes



Oct 07, 2007: Prototype tests. Tpw=50ns


Dec 07: The original design cleared the time gate with the trigger pulse (U16D-13 connected to Trigger from U17B-5). This was changed as the result of a discussion with Jimmy and Bobby. The change leaves the gate active until time-out.


Feb 08: Following PSpice simulations it was noted that the trigger was missing every other signal input which was meeting the window requirement. The raw trigger was connected so as to clear the gate register (Raw Trigger connected to CLR line of Gate register U3A through U16D and U5B. Raw triggers are now 200 ns wide.


Feb 11: The decision was make to add a trigger mode switch which will switch the TRIGGER Output connector between the RAW Trigger and the GLOBAL Trigger. The EXTERNAL Trigger input was changed so that it will generate a RAW Trigger. The RAW Trigger will be stretched from the current 0.2uS to 10uS in order to facilitate the front panel TRIGGER LED feature.


Oct 10,2008: Two four layer printed circuit boards were designed and fabricated for use at Sudan, one of the modules will be used as a spare. Module SN1 has completed assembly and has gone through final checkout. One difference between these final versions and the prototype is the USB Trigger IN and USB Trigger Enable are switched which will require a small software change to the to switch these features.

Modified the NIM/CMOS converter stage to reduce the pulse storage time by 57% and the delay time by 12% (ie Td=16ns, Tw=65ns, with Twin=53ns). This was accomplished by reducing R10 and R11 by a factor of 10 thereby increasing the Q1 collector current by 10.

The frequency setup resistor R12, for the oscillator U19, was changed from a fixed value of 8.2k to a 10 k pot for ease of the event window time calibration (10 <T<150uS).


November 12, 2008: A triggering problem was discovered when a very fast sequence of input pulses are introduced to the trigger module. A false trigger is sometimes generated when a double pair of short ~40 nS pulses appear at the input. An example of a false trigger might occur when the setup is for 3 events in 100 uS and the double pair causes a trigger. The cause of the problem was traced to the pulse counter U11 which is a Fairchild MM74HC4040M binary counter with a typical clock limit of 50 mHz (1/20nS). The counter was replaced with a NXP 74HC4040D with a typical clock limit of 98 mHz (1/10.2nS). With the faster counter the problem has been resolved.


3 December 2008: The Trigger Enable switch is marked in reverse on the panel (ie. Use and Ignore are switched).


17 December 2008: The prototype module has been changed to be the same as SN1 and SN2 with regards to the switched USB Trigger IN and the USB Trigger Enable. The posted schematic for the prototype has been undated.


14 January 2009: The raw trigger normaly terminates at the end of the gate window, however it may be terminated early by subsequent input pulses as illustrated in PSpice Simulation2. Additional triggers may also be generated prior to the termination of the gate window, this is also illustrated in the simulation. This has not created any system problems so the behavior has not been corrected.