CDMS2  RTF 9U Trigger

Electronics Documentation

Under Construction, note updates

Trigger Conditioner Boards:


            Trigger Conditioner  board layout :     TCLrevB.pdf   and   TCRrevC.pdf    6/16/07  


Trigger Logic Board:




      1. TLNIZIP161.mcs   Fixed Mode 0  __9/10/2010
      2. TLNIZIP162.mcs   Fixed Mode 1
      3. TLNIZIP163.mcs   Fixed Mode 2
      4. TLNIZIP171.mcs   Operational EPRM, Default Mode is 3 __12/24/2010








Under Construction 4/18/07





 Wisper Triggers will be generated by monitoring for a multiple Wisper sequence within an 18 microsecond time frame and creating a Global Trigger through a new Trigger Mode Function (WSPTRIG). This new Wisper Trigger will be OR’d with the other Triggers.  The Wisper sequence can be selected at 3, 4 or 5, the default is off. The Wisper triggers will be stretched from 1 to 18 microseconds in the Trigger Conditioners.



Each Trigger Conditioner board has 3 fpga’s which receive only two Tower Detector Channels (ie. Q1h, Q1l, P1h, P1l, W1, Q2h, Q2l, P2h, P2l, W2) .  In order for the FPGA algorithm to be able to control the TimeStamp (T/S) channel, additional Detector Channels must be sent to each fpga. This will be accomplished by using the two unused detector input channels which each fpga currently has (ie. UU1, UU2). For fpga#1 one of the unused channels will be jumpered to Wisper channel W3 which is available at the RTF connector via array as illustrated. Unused channel 2 will be connected to ground.  A new faster flashing LED code will be used for this update. The T/S channel will be turned on when a 3 Wisper sequence is detected within the 18 microsecond time window.  The T/S channel which previously was routed to Wisper trigger lines will now route to the AND function of a 3 Wisper sequence (see TrigCond3.pdf ). Note that the Wisper Trigger outputs from the Conditioner board are now stretched to 18 us but the Time Stamp outputs (W1 and W2 and W3) are 1 us.






Old Configuration                                New Configuration


Tower A Left

      W1      TSA14             A4                   W1*W2*W3               TSA14                        A4

      W2      TSA19             A9                   W1*W2*0                   TSA19                        A9       Inactive

      W3      TSA24             A14                 W2*W3*W4                TSA24                        A14

      W4      TSA29             A19                 W3*W4*W5               TSA29                        A19

      W5      TSA34             A24                 W4*W5*W6               TSA34                        A24

      W6      TSA39             A29                 W5*W6*0                   TSA39                        A29     Inactive

Tower B Right

      W1      TSB14 B4                   W1*W2*W3               TSB14             B4

      W2       Etc …………..                      





Wisper Modification Record (Rev C)   4/18/07


TYPE        Serial Nr    Revision       Wisper Change         Location                          Notes


Right          Ser 02                 tbd                     No                          tbd

Right          Ser 03                 C                      Yes                          Sudan               Trig out jumpers added for Rev B        

Right          Ser 04                 B                       No                           tbd

Right          Ser 05                 B                       No                           tbd

Right          Ser 06                 B                       No                           tbd

Right          Ser 07                 B                       No                           tbd


Left            Ser 01                A                      No                           UCSB                Old layout

Left            Ser 08                 C                      Yes                          Sudan       first board modified and tested

Left            Ser 09                 B                       No                           tbd

Left            Ser 10                 C                      Yes                          Sudan        Corrected soldering problem re P2L

Left            Ser 11                 B                       No                           tbd

Left            Ser 12                 C                      Yes                          Sudan       Sent back from Sudan with problem

Left            Ser 13                 B                       No                           tbd

Left            Ser 14                 B                       No                           tbd



NOTE: Time stamp channels A30, A31, B30 and B31 jumpered to Trigger Logic Connector on board to implement GTO, RAND, ISR and (ST+TE) is Revision B or lator on  Trigger Conditioner board.


CDMS IZIP Trigger Scheme


    The trigger scheme for CDMS Towers contining the new iZIP Detectors will be significiantly different.  Each iZIP Detector uses twic as many Phonon and Ionization Channels, however the electronics boards (FEB's and RTF boards) remain unaltered.  Therefore, the trigger logic board will now receive twice the number of logic levels for each detector: two sets of Phonon Low Logic Levels, etc.  Each of the two Phonon Low Logic Levels indicate wheather the combined Phonon Signals from half the Phonon Channels on an iZIP are over a user-specified Low Threshold.

    Currently the TLB vews each of these phonon low lgic levels (likewise for the other pairs of logic levels) as if they were coming from different detectors.  Therefore, we are updating the TLB Trigger Logic to treat both pairs of logic levels as if they were coming from the same detector. The difficulty in doing this is that the TLB Trigger Logic  for one detector is handled seperately for the trigger logic for another detector.

    The triggering fgor the ionization channels will require little change.  We will replace the high trigger or lo not high trigger with a low AND trigger. The low AND trigger will trigger on the AND of the two iZIP low triggers.

    The triggering for the phonon channels will require more significant modificaion. The four trigger modes will be low OR, low AND, low OR with the nearest neighbor, and low AND with nearest neighbor.

    The low OR trigger is simply the current trigger mode 3 - trigger on the OR of all phonon low levels.

    The low AND trigger requires triggering on the AND of an iZIP's two phonon low logic levels.

    The low OR trigger with the nearest neighbor trigger mode is identical to the low OR trigger with the additional requirement that an adjacent detector asso satisfy the low OR requirement.

    The low AND with the nearest neighbor trigger mode is likewise identical to the lwo AND trigger with the additional requirement that an adjacent detector also satisfy the low AND requirement.

    The tabulation below representations of the four new trigger modes for the first iZIP where U2, U4, U6, etc is the phonon low logical pulse for the first half of the thest iZIP, second half the first iZIP , first half of the second iZIP, etc:

    MODE #2 ---  iZIP AND                               

    AND of U2 & U4                                                LO2IN   AND  LOTRIGIN

    MODE #3 ---   iZIP OR

    No change from the current mode 3                     LOTRIGIN

    MODE #0  ----  iZIP AND With Near Neighbor

    1)  AND of U2 and U4                                 [LOTRIGIN ANDLO2IN AND (NEAR 0 AND NEAR 1) OR

    2)  AND of U6 and U8                                     (NEAR 2 AND NEAR 3) ]

    3)  AND of 1) and 2)

    MODE #1 -----  iZIP OR With Near Neighbor . .  . . ( In process SPB) __1/28/2011





Trigger Board Manufacturing Schedule: and Trigschedule1.pdf    _7/26/00

Direct comments or questions to:     Updated 28 January 20101 SPB